2.7.4.5 MPU Region Attribute and Size Register

The MPU_RASR defines the region size and memory attributes of the MPU region specified by the MPU_RNR, and enables that region and any subregions. See the register summary in Table 2-71 for its attributes.

MPU_RASR is accessible using word or halfword accesses:

  • the most significant halfword holds the region attributes
  • the least significant halfword holds the region size and the region and subregion enable bits.

The bit assignments are:

Figure 2-49. MPU_RASR Bit Assignments
Table 2-76. MPU_RASR Bit Assignments
BitsNameFunction
[31:29]Reserved.
[28]XNInstruction access disable bit:

0: instruction fetches enabled

1: instruction fetches disabled.

[27]Reserved.
[26:24]APAccess permission field, see Table 2-80.
[23:22]Reserved.
[21:19, 17, 16]TEX, C, BMemory access attributes, see Table 2-78.
[18]SShareable bit, see Table 2-78.
[15:8]SRDSubregion disable bits. For each bit in this field:

0: corresponding sub-region is enabled

1: corresponding sub-region is disabled

See Subregions for more information.

Region sizes of 128 bytes and less do not support subregions. When writing the attributes for such a region, write the SRD field as 0x00.

[7:6]Reserved.
[5:1]SIZESpecifies the size of the MPU protection region. The minimum permitted value is 3 (b00010), see See SIZE Field Values for more information.
[0]ENABLERegion enable bit.

For information about access permission, refer to MPU Access Permission Attributes.