2.7.1 About the Cortex-M3 Processor Peripherals

The following table provides the address map of the Private peripheral bus (PPB).

Table 2-33. Core Peripheral Register Regions
AddressCore PeripheralSee
0xE000E008-0xE000E00FSystem control blockTable 2-44
0xE000E010-0xE000E01FSystem timerTable 2-65
0xE000E100-0xE000E4EFNested Vectored Interrupt ControllerTable 2-34
0xE000ED00-0xE000ED3FSystem control blockTable 2-44
0xE000ED90-0xE000ED93MPU Type Register

Reads as zero, indicating no MPU is implemented1

0xE000ED90-0xE000EDB8Memory protection unitTable 2-71
0xE000EF00-0xE000EF03Nested Vectored Interrupt ControllerTable 2-34
Note:
  1. Software can read the MPU Type Register at 0xE000ED90 to test for the presence of a memory protection unit (MPU).

In register descriptions:

  • the register type is described as follows:
    • RW: Read and write.
    • RO: Read-only.
    • WO: Write-only.
  • the required privilege gives the privilege level required to access the register, as follows:
    • Privileged: Only privileged software can access the register.
    • Unprivileged: Both unprivileged and privileged software can access the register.