2.7.1 About the Cortex-M3 Processor Peripherals

The following table provides the address map of the Private peripheral bus (PPB).

Table 2-33. Core Peripheral Register Regions
Address	Core Peripheral	See
0xE000E008-0xE000E00F	System control block	Table 2-44
0xE000E010-0xE000E01F	System timer	Table 2-65
0xE000E100-0xE000E4EF	Nested Vectored Interrupt Controller	Table 2-34
0xE000ED00-0xE000ED3F	System control block	Table 2-44
0xE000ED90-0xE000ED93	MPU Type Register	Reads as zero, indicating no MPU is implemented¹
0xE000ED90-0xE000EDB8	Memory protection unit	Table 2-71
0xE000EF00-0xE000EF03	Nested Vectored Interrupt Controller	Table 2-34

Note:

Software can read the MPU Type Register at 0xE000ED90 to test for the presence of a memory protection unit (MPU).

In register descriptions:

the register type is described as follows:
- RW: Read and write.
- RO: Read-only.
- WO: Write-only.
the required privilege gives the privilege level required to access the register, as follows:
- Privileged: Only privileged software can access the register.
- Unprivileged: Both unprivileged and privileged software can access the register.

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