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SmartFusion 2 Microcontroller Subsystem
SmartFusion 2 Microcontroller Subsystem
  1. Home
  2. 2 Cortex-M3 Processor (Reference Material)
  3. 2.7 Cortex-M3 Processor Peripherals
  4. 2.7.4 Memory Protection Unit
  5. 2.7.4.7 MPU Mismatch
  • Introduction
  • 1 Cortex-M3 Processor Overview and Debug Features
  • 2 Cortex-M3 Processor (Reference Material)
    • 2.1 System Level Interface
    • 2.2 Integrated Configurable Debug
    • 2.3 Cortex-M3 Processor Features and Benefits Summary
    • 2.4 Cortex-M3 Processor Core Peripherals
    • 2.5 Cortex-M3 Processor Description
    • 2.6 Cortex-M3 Processor Instruction Set
    • 2.7 Cortex-M3 Processor Peripherals
      • 2.7.1 About the Cortex-M3 Processor Peripherals
      • 2.7.2 System Control Block
      • 2.7.3 System Timer, SysTick
      • 2.7.4 Memory Protection Unit
        • 2.7.4.1 MPU Type Register
        • 2.7.4.2 MPU Control Register
        • 2.7.4.3 MPU Region Number Register
        • 2.7.4.4 MPU Region Base Address Register
        • 2.7.4.5 MPU Region Attribute and Size Register
        • 2.7.4.6 MPU Access Permission Attributes
        • 2.7.4.7 MPU Mismatch
        • 2.7.4.8 Updating an MPU Region
        • 2.7.4.9 MPU Design Hints and Tips
  • 3 Cache Controller
  • 4 Embedded NVM (eNVM) Controllers
  • 5 Embedded SRAM (eSRAM) Controllers
  • 6 AHB Bus Matrix
  • 7 High Performance DMA Controller
  • 8 Peripheral DMA
  • 9 Universal Serial Bus On-The-Go Controller
  • 10 Ethernet MAC
  • 11 CAN Controller
  • 12 MMUART Peripherals
  • 13 Serial Peripheral Interface Controller
  • 14 Inter-Integrated Circuit Peripherals
  • 15 MSS GPIO
  • 16 Communication Block
  • 17 RTC System
  • 18 System Timer
  • 19 Watchdog Timer
  • 20 Reset Controller
  • 21 System Register Block
  • 22 Fabric Interface Interrupt Controller
  • 23 Fabric Interface Controller
  • 24 APB Configuration Interface
  • 25 Error Detection and Correction Controllers
  • 26 Revision History
  • Microchip FPGA Support
  • Microchip Information

2.7.4.7 MPU Mismatch

When an access violates the MPU permissions, the processor generates a MemManage fault, see 2.5.1.4 Exceptions and Interrupts. The MMFSR indicates the cause of the fault. See 2.7.2.17 Auxiliary Fault Status Register for more information.

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.

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