10.5.1 SGMII Interface Configuration

  1. Select the interface as TBI, line speed as required. Enable the management interface check box as shown in the following figure.
    Figure 10-8. MSS Ethernet Configurator with TBI Interface
  2. Connect TBI signals to SerDes, which is configured for EPCS mode, as shown in the following figure.
    Figure 10-9. SGMII Interface Signals: TBI to SerDes
    Important: Timing models for SerDes to Fabric have been updated with additional time delay. This changes the timing arcs of nets and interface between SerDes to Fabric Nets. To meet timing accuracy, open all Libero v11.7 SP3 designs and re-run Verify Timing. If you get new timing violations, do the following:
    1. Re-run place-and-route.
    2. Re-run place-and-route with high effort.
    3. Run place-and-route with multi-pass.
    4. Adjust timing constraints or use chip planner to floorplan the affected interfaces.

      For more information about the updated timing arcs, see PCN 17005A.

  3. In design flow window of Libero SoC under compile option open Edit I/O attributes option and assign pin names to PHY interface as shown in the following figure.
    Figure 10-10. I/O Editor With SGMII and PHY Ports