8.4.1.4 CHANNEL_x_STATUS Register Bit Definition
| Bit Number | Name | Reset Value | Description |
|---|---|---|---|
| [31:3] | Reserved | 0 | Software must not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit must be preserved across a read-modify-write operation. |
| 2 | BUF_SEL | 0 | 0: Buffer A is used 1: Buffer B is used |
| 1 | CH_COMP_B | 0 | Asserts when this channel completes its DMA. Cleared by writing to CLR_COMP_B, bit 8 in CHANNEL_x_CONTROL register for this channel. If INTEN is set for this channel, the assertion of CH_COMP_B causes PDMAINTERRUPT to assert. |
| 0 | CH_COMP_A | 0 | Asserts when this channel completes its DMA. Cleared by writing to CLR_COMP_A, bit 8 in CHANNEL_x_CONTROL register for this channel. If INTEN is set for this channel, the assertion of CH_COMP_A causes PDMAINTERRUPT to assert. |