8.4.1.8 CHANNEL_x_BUFFER_B_SRC_ADDR Register Bit Definition

Table 8-13. CHANNEL_x_BUFFER_B_SRC_ADDR
Bit Number	Name	Reset Value	Description
[31:0]	BUF_B_SRC	0	Start address from which data is to be read during the next DMA transfer cycle. If PERIPHERAL_DMA = 1 and DIR = 0, this value is not incremented from one DMA transfer cycle to the next. Otherwise, it is always incremented by an amount corresponding to the TRANSFER_SIZE for this channel.

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