8.4.1.5 CHANNEL_x_BUFFER_A_SRC_ADDR Register Bit Definition
| Bit Number | Name | Reset Value | Description |
|---|---|---|---|
| [31:0] | BUF_A_SRC | 0 | Start address from which data is to be read during the next DMA transfer cycle. If PERIPHERAL_DMA = 1 and DIR = 0, this value is not incremented from one DMA transfer cycle to the next. Otherwise, it is always incremented by an amount corresponding to the TRANSFER_SIZE for this channel. |