8.4.1.7 CHANNEL_x_BUFFER_A_TRANSFER_COUNT Register Bit Definition

Table 8-12. CHANNEL_x_BUFFER_A_TRANSFER_COUNT
Bit Number Name Reset Value Description
[31:16] Reserved 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
[15:0] BUF_A_COUNT 0 Number of remaining transfers to be completed between source and destination for buffer A for this channel. This field is decremented after every DMA transfer cycle.

Writing a non-zero value to this register causes the DMA to start. This must be the last register written by firmware when setting up a DMA transfer.