3.2.3.3 Cache Engine

The Cache Engine takes care of address generation logic using a four-way set associative, hit and miss generation logic, cache line filling/replacement, a temporary local buffer for cache line while writing, and arbitration logic for ICode and DCode buses.

The Cache Controller has a four-way set associative cache subsystem with 32-byte cache lines organized as 64 sets of 4 cache lines. Eight bits from the memory address (shown in the following figure) select one of these 256 different locations. The Cache Controller can map a block of 32 data bytes to any of the cache lines, replacing the LRU block. As one location of the memory contains 64-bit information the required data can be selected by using the second bit from the memory address as shown in the figure.

The Cache Engine has two buses interacting with the ICode and DCode buses through interfaces MS3 and MS4. It supports the following functionalities:

1. Only read transfers from ICode and DCode bus are cached
2. 32 bytes local buffering of cache line read from slave
3. Support 32-/128-bit local interface on the AHB master side
4. All miss non-cacheable transactions targeted for eNVM are routed through MM4
5. Arbitration: In case of simultaneous access from ICode and DCode, all transactions from DCode are processed before ICode is processed.
   • a. Supports full cache flush or index-based flushing
   • b. Supports hit/miss generation mechanism for Cache Memory and local buffer
   • c. One of the following types of transaction will come to the Cache Engine:
     • Transaction for cacheable region in DDR
     • Transaction for non-cacheable region in DDR
     • Transaction for cacheable region in eNVM
6. Supports Cache Disable mode where all transactions will be treated as non-cacheable and replicated “as is” on DDR or switch-side