If any master attempts a write access to an unimplemented address space, the cache matrix completes the handshake with the master, with HRESP error indication. No write occurs to any slave.
If any master attempts a read access from an unimplemented address space, the cache matrix completes the handshake with the master, with HRESP error indication. Garbage data is returned in this case.
The cache matrix supports locked transactions from the SBUS towards
the eSRAM AHB controller, through the switch, by monitoring HMASTLOCK. The cache matrix
initiates IDLE on the AHB bus after every LOCKED transfer. SmartFusion2 SoC FPGA - Cache Controller Configuration Application
Note
The cache matrix handshakes correctly with masters performing AHB-Lite bursts to any slave. The ICache slave on the cache matrix supports bursts from the cache master.
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
