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SmartFusion 2 Microcontroller Subsystem
SmartFusion 2 Microcontroller Subsystem
  1. Home
  2. 2 Cortex-M3 Processor (Reference Material)
  3. 2.6 Cortex-M3 Processor Instruction Set
  4. 2.6.5 General Data processing instructions
  5. 2.6.5.5 CMP and CMN
  6. 2.6.5.5.1 Syntax
  • Introduction
  • 1 Cortex-M3 Processor Overview and Debug Features
  • 2 Cortex-M3 Processor (Reference Material)
    • 2.1 System Level Interface
    • 2.2 Integrated Configurable Debug
    • 2.3 Cortex-M3 Processor Features and Benefits Summary
    • 2.4 Cortex-M3 Processor Core Peripherals
    • 2.5 Cortex-M3 Processor Description
    • 2.6 Cortex-M3 Processor Instruction Set
      • 2.6.1 Instruction Set Summary
      • 2.6.2 CMSIS Functions
      • 2.6.3 About the Instruction Descriptions
      • 2.6.4 Memory Access Instructions
      • 2.6.5 General Data processing instructions
        • 2.6.5.1 ADD, ADC, SUB, SBC, and RSB
        • 2.6.5.2 AND, ORR, EOR, BIC, and ORN
        • 2.6.5.3 ASR, LSL, LSR, ROR, and RRX
        • 2.6.5.4 CLZ
        • 2.6.5.5 CMP and CMN
          • 2.6.5.5.1 Syntax
          • 2.6.5.5.2 Operation
          • 2.6.5.5.3 Restrictions
          • 2.6.5.5.4 Condition Flags
        • 2.6.5.6 MOV and MVN
        • 2.6.5.7 MOVT
        • 2.6.5.8 REV, REV16, REVSH, and RBIT
        • 2.6.5.9 TST and TEQ
      • 2.6.6 Multiply and Divide Instructions
      • 2.6.7 Saturating Instructions
      • 2.6.8 Bitfield instructions
      • 2.6.9 Branch and Control Instructions
      • 2.6.10 Miscellaneous Instructions
    • 2.7 Cortex-M3 Processor Peripherals
  • 3 Cache Controller
  • 4 Embedded NVM (eNVM) Controllers
  • 5 Embedded SRAM (eSRAM) Controllers
  • 6 AHB Bus Matrix
  • 7 High Performance DMA Controller
  • 8 Peripheral DMA
  • 9 Universal Serial Bus On-The-Go Controller
  • 10 Ethernet MAC
  • 11 CAN Controller
  • 12 MMUART Peripherals
  • 13 Serial Peripheral Interface Controller
  • 14 Inter-Integrated Circuit Peripherals
  • 15 MSS GPIO
  • 16 Communication Block
  • 17 RTC System
  • 18 System Timer
  • 19 Watchdog Timer
  • 20 Reset Controller
  • 21 System Register Block
  • 22 Fabric Interface Interrupt Controller
  • 23 Fabric Interface Controller
  • 24 APB Configuration Interface
  • 25 Error Detection and Correction Controllers
  • 26 Revision History
  • Microchip FPGA Support
  • Microchip Information

2.6.5.5.1 Syntax

CMP{cond} Rn, Operand2

CMN{cond} Rn, Operand2

where:

cond is an optional condition code, see 2.6.3.7 Conditional Execution.

Rn is the register holding the first operand.

Operand2 is a flexible second operand. See 2.6.3.3 Flexible Second Operand for details of the options.

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.

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