2.6.5.1.3 Restrictions

In these instructions:

Operand2 must not be SP and must not be PC
Rd can be SP only in ADD and SUB, and only with the additional restrictions:
- Rn must also be SP
- Any shift in Operand2 must be limited to a maximum of 3 bits using LSL
Rn can be SP only in ADD and SUB
Rd can be PC only in the ADD{cond} PC, PC, Rm instruction where:
- You must not specify the S suffix
- Rm must not be PC and must not be SP
- If the instruction is conditional, it must be the last instruction in the IT block
with the exception of the ADD{cond} PC, PC, Rm instruction, Rn can be PC only in ADD and SUB, and only with the additional restrictions:
- You must not specify the S suffix
- The second operand must be a constant in the range 0 to 4095
- When using the PC for an addition or a subtraction, bits[1:0] of the PC are rounded to b00 before performing the calculation, making the base address for the calculation word-aligned.
- If you want to generate the address of an instruction, you have to adjust the constant based on the value of the PC. Arm recommends that you use the ADR instruction instead of ADD or SUB with Rn equal to the PC, because your assembler automatically calculates the correct constant for the ADR instruction.

When Rd is PC in the ADD{cond} PC, PC, Rm instruction: