12.2.3.4 Interrupts

There is one interrupt signal from each MMUART peripheral. The MMUART_0_INT signal is generated by MMUART_0 and is mapped to INTISR[10] in the Cortex-M3 processor Nested Vectored Interrupt Controller (NVIC). The MMUART_1_INT signal is generated by MMUART_1 and is mapped to INTISR[11] in the Cortex-M3 processor NVIC. Both interrupt enable bits within NVIC-INTISR[10] and INTISR[11] correspond to bit locations 10 and 11. MMUART interrupts are enabled by setting the appropriate bits in the IER register while the divisor latch access bit of Table 12-17 (Table 12-17) is 0. Ensure the clearing of the appropriate bit in the IER interrupt service routine to prevent a re-assertion of the interrupt.