12.2.3.3 Clock Requirements

The MMUART_0 and MMUART _1 peripherals are clocked by APB_0_CLK on APB bus 0 and APB_1_CLK on APB bus 1. These clocks are derived from the main MSS clock M3_CLK. Each APB clock can be programmed individually as M3_CLK divided by 1, 2, 4, or 8. For more information on clocks, see
 UG0449: SmartFusion2 and IGLOO2 Clocking Resources User Guide.

The baud rate generator block receives the input from APB clock and divides by the value of the Baud Rate Registers (Table 12-8, Table 12-9, and Table 12-10). The result is then divided further by 16 to produce the integer baud rate. The resultant signal is the BAUDOUT signal. The MMUART also has a fractional baud rate generation capability. These features are described in detail in 12.2.4.1 Baud Rate Generation.