12.4.10 Line Control Register (LCR)
| Bit Number | Name | R/W | Reset Value | Description |
|---|---|---|---|---|
| 7 | DLAB | R/W | 0 | Divisor latch access bit. Enables access to the divisor latch registers during read or write operation to address 0 and 1. 0: Disabled (default) 1: Enabled |
| 6 | SB | R/W | 0 | Set break. Enabling this bit sets MMUART_x_TXD to 0. This does not have any effect on transmitter logic. The break is disabled by setting the bit to 0. 0: Disabled (default) 1: Set break |
| 5 | SP | R/W | 0 | Stick parity 0: Disabled (default) 1: Enabled When stick parity is enabled, the parity is set according to bits [4:3] as follows: 11: 0 will be sent as a parity bit and checked when receiving. 01: 1 will be sent as a parity bit and checked when receiving. |
| 4 | EPS | R/W | 0 | Even parity select 0: Odd parity (default) 1: Even parity |
| 3 | PEN | R/W | 0 | Parity enable 0: Disabled 1: Enabled. Parity is added in transmission and checked in receiving. |
| 2 | STB | R/W | 0 | Number of stop bits (STB) 0: 1 stop bit (default) 1: 11/2 stop bits when WLS = 00 The number of stop bits is 2 for all other cases not described above (STB = 1 and WLS = 01, 10, or 11). |
| [1:0] | WLS | R/W | 0 | Word length select 0b00: 5 bits (default) 0b01: 6 bits 0b10: 7 bits 0b11: 8 bits |