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SmartFusion 2 Microcontroller Subsystem

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2 Cortex-M3 Processor (Reference Material)
2.6 Cortex-M3 Processor Instruction Set
2.6.4 Memory Access Instructions
2.6.4.4 LDR and STR, Unprivileged
2.6.4.4.3 Restrictions

Introduction
1 Cortex-M3 Processor Overview and Debug Features
2 Cortex-M3 Processor (Reference Material)
3 Cache Controller
4 Embedded NVM (eNVM) Controllers
5 Embedded SRAM (eSRAM) Controllers
6 AHB Bus Matrix
7 High Performance DMA Controller
8 Peripheral DMA
9 Universal Serial Bus On-The-Go Controller
10 Ethernet MAC
11 CAN Controller
12 MMUART Peripherals
13 Serial Peripheral Interface Controller
14 Inter-Integrated Circuit Peripherals
15 MSS GPIO
16 Communication Block
17 RTC System
18 System Timer
19 Watchdog Timer
20 Reset Controller
21 System Register Block
22 Fabric Interface Interrupt Controller
23 Fabric Interface Controller
24 APB Configuration Interface
25 Error Detection and Correction Controllers
26 Revision History
Microchip FPGA Support
Microchip Information

2.6.4.4.3 Restrictions

In these instructions:

Rn must not be PC.
Rt must not be SP and must not be PC.

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