23.7.2 Configuring the FIC Subsystem Clocks

To create the proper clock configuration and connectivity you must:

  • Configure the MSS CCC FIC clocks.
  • Instantiate and configure an FPGA fabric CCC core.
  • Connect the clock networks for each FIC subsystem.
  • Connect the MSS CLK_BASE port to the correct FPGA fabric FIC subsystem clock network.

The SmartFusion 2 architecture imposes the following rules that must be followed for synchronous communication between the MSS and the FPGA fabric FIC subsystems. The following figure illustrates these rules.

  • Each FPGA fabric FIC subsystem must be driven by a clock whose frequency matches the frequency defined, for that particular subsystem, in the MSS_CCC configurator.
  • All the FPGA fabric FIC subsystem clocks must be precisely aligned; the clocks may be of different frequencies, but the rising edges of the slower clocks must be aligned to the rising edges of the fastest clocks.
  • The FPGA fabric FIC subsystem clock with the smallest frequency must drive the MSS CLK_BASE.
  • If a fabric PLL is used, then the fabric PLL’s LOCK output must be connected to the MSS_CCC_CLK_BASE_PLL_LOCK port, for fabric PLL lock monitoring.
Figure 23-24. Clocking Scheme for Synchronous Communication Between the MSS and the FPGA Fabric

The following steps describe how to configure the clock networks for all FIC subsystems.