23.7.4.1 Use Model 1: Connecting an MSS Master to the Fabric AHB-Lite Slave Interface

The following figure shows a MSS master and fabric slave scenario. The MSS acts as an AHB-Lite master for Registered or Bypass mode. The Cortex-M3 processor master, or any other master on the AHB bus matrix in the MSS, can access the AHB-Lite slaves in the fabric through FIC_0 or FIC_1. CoreAHBLite gives the HREADY and HSEL signals connectivity to the fabric AHB-Lite slaves. The MSS master AHB-Lite interface passes all incoming AHB-Lite transactions to the fabric with no error checking. If an error has occurred during the transfer, the fabric AHB-Lite slaves must signal the error condition to the master so that it is aware the transfer has been unsuccessful.

Figure 23-28. AHB-Lite Slaves in the FPGA Fabric Connected to the MSS Master

The following tutorial describes this Use Model with a design example: TU0310: Interfacing User Logic with the Microcontroller Subsystem - Libero SoC Design Flow Tutorial.

This tutorial describes how to interface and handle communication between the user logic in the FPGA fabric and the MSS. The MSS is configured with FIC_0 and FIC_1 enabled. FIC_0 is configured for the AHBL master interface and connected to CoreAHBLSRAM salve. FIC_1 is configured for the APB3 master interface and connected to CoreGPIO slave.