2.6.6.3.1 Syntax

SDIV{cond} {Rd,} Rn, Rm
UDIV{cond} {Rd,} Rn, Rm

where:

cond is an optional condition code, see 2.6.3.7 Conditional Execution.

Rd is the destination register. If Rd is omitted, the destination register is Rn.

Rn is the register holding the value to be divided.

Rm is a register holding the divisor.

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