38.7.7 LCD Controller Configuration Register 6
| Name: | LCDC_LCDCFG6 |
| Offset: | 0x18 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PWMCVAL[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PWMPOL | PWMPS[2:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
Bits 15:8 – PWMCVAL[7:0] LCD Controller PWM Compare Value
PWM compare value. Used to adjust the analog value obtained after an external filter to control the contrast of the display.
Bit 4 – PWMPOL LCD Controller PWM Signal Polarity
This bit defines the polarity of the PWM output signal.
| Value | Description |
|---|---|
| 0 | The output pulses are low level. |
| 1 | The output pulses are high level (the output is high whenever the value in the counter is less than value CVAL). |
Bits 2:0 – PWMPS[2:0] PWM Clock Prescaler
Selects the configuration of the counter prescaler module.
| Value | Name | Description |
|---|---|---|
| 000 | DIV_1 | The counter advances at a rate of fCOUNTER = fPWM_SELECTED_CLOCK |
| 001 | DIV_2 | The counter advances at a rate of fCOUNTER = fPWM_SELECTED_CLOCK/2 |
| 010 | DIV_4 | The counter advances at a rate of fCOUNTER = fPWM_SELECTED_CLOCK/4 |
| 011 | DIV_8 | The counter advances at a rate of fCOUNTER = fPWM_SELECTED_CLOCK/8 |
| 100 | DIV_16 | The counter advances at a rate of fCOUNTER = fPWM_SELECTED_CLOCK/16 |
| 101 | DIV_32 | The counter advances at a of rate fCOUNTER = fPWM_SELECTED_CLOCK/32 |
| 110 | DIV_64 | The counter advances at a of rate fCOUNTER = fPWM_SELECTED_CLOCK/64 |