38.7.9 LCD Controller Enable Register
| Name: | LCDC_LCDEN |
| Offset: | 0x20 |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PWMEN | DISPEN | SYNCEN | CLKEN | ||||||
| Access | W | W | W | W | |||||
| Reset | – | – | – | – |
Bit 3 – PWMEN LCD Controller Pulse Width Modulation Enable
| Value | Description |
|---|---|
| 0 | No effect |
| 1 | PWM is enabled. |
Bit 2 – DISPEN LCD Controller DISP Signal Enable
| Value | Description |
|---|---|
| 0 | No effect |
| 1 | LCDDISP signal is generated. |
Bit 1 – SYNCEN LCD Controller Horizontal and Vertical Synchronization Enable
| Value | Description |
|---|---|
| 0 | No effect |
| 1 | Both horizontal and vertical synchronization (LCDVSYNC and LCDHSYNC) signals are generated. |
Bit 0 – CLKEN LCD Controller Pixel Clock Enable
| Value | Description |
|---|---|
| 0 | No effect |
| 1 | Pixel clock logical unit is activated. |