The following
configuration values are valid for all listed bit names of this register:
0: No effect.
1: Disables the corresponding interrupt.
Name:
LCDC_HEOIDR
Offset:
0x00000370
Reset:
–
Property:
Write-only
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
VOVR
VDONE
VADD
VDSCR
VDMA
Access
W
W
W
W
W
Reset
–
–
–
–
–
Bit
15
14
13
12
11
10
9
8
UOVR
UDONE
UADD
UDSCR
UDMA
Access
W
W
W
W
W
Reset
–
–
–
–
–
Bit
7
6
5
4
3
2
1
0
OVR
DONE
ADD
DSCR
DMA
Access
W
W
W
W
W
Reset
–
–
–
–
–
Bit 22 – VOVR Overflow for V Chrominance Component Interrupt
Disable
Bit 21 – VDONE End of List for V Chrominance Component Interrupt
Disable
Bit 20 – VADD Head Descriptor Loaded for V Chrominance Component
Interrupt Disable
Bit 19 – VDSCR Descriptor Loaded for V Chrominance Component
Interrupt Disable
Bit 18 – VDMA End of DMA Transfer for V Chrominance Component
Interrupt Disable
Bit 14 – UOVR Overflow Interrupt for U or UV Chrominance
Component Disable
Bit 13 – UDONE End of List Interrupt for U or UV Chrominance
Component Disable
Bit 12 – UADD Head Descriptor Loaded for U or UV Chrominance
Component Interrupt Disable
Bit 11 – UDSCR Descriptor Loaded for U or UV Chrominance Component
Interrupt Disable
Bit 10 – UDMA End of DMA Transfer for U or UV Chrominance
Component Interrupt Disable
Bit 6 – OVR Overflow Interrupt
Disable
Bit 5 – DONE End of List Interrupt
Disable
Bit 4 – ADD Head Descriptor Loaded Interrupt
Disable
Bit 3 – DSCR Descriptor Loaded Interrupt
Disable
Bit 2 – DMA End of DMA Transfer Interrupt
Disable
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