38.7.4 LCD Controller Configuration Register 3

Name:	LCDC_LCDCFG3
Offset:	0x0C
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
							HBPW[9:8]
Access							R/W	R/W
Reset							0	0


Bit	23	22	21	20	19	18	17	16
	HBPW[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
							HFPW[9:8]
Access							R/W	R/W
Reset							0	0


Bit	7	6	5	4	3	2	1	0
	HFPW[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 25:16 – HBPW[9:0] Horizontal Back Porch Width

Number of pixel clock cycles inserted at the beginning of the line. The interval is equal to (HBPW+1) LCDPCLK cycles.

Bits 9:0 – HFPW[9:0] Horizontal Front Porch Width

Number of pixel clock cycles inserted at the end of the active line. The interval is equal to (HFPW+1) LCDPCLK cycles.

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