The following
configuration values are valid for all listed bit names of this register:
0: No effect.
1: Disables the corresponding interrupt.
Name:
LCDC_LCDIDR
Offset:
0x30
Reset:
–
Property:
Write-only
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
Access
Reset
Bit
15
14
13
12
11
10
9
8
PPID
HEOID
OVR2ID
OVR1ID
BASEID
Access
W
W
W
W
W
Reset
–
–
–
–
–
Bit
7
6
5
4
3
2
1
0
FIFOERRID
ROWID
DISPID
DISID
SOFID
Access
W
W
W
W
W
Reset
–
–
–
–
–
Bit 13 – PPID Post Processing Interrupt
Disable
Bit 11 – HEOID High-End Overlay Interrupt
Disable
Bit 10 – OVR2ID Overlay 2 Interrupt
Disable
Bit 9 – OVR1ID Overlay 1 Interrupt
Disable
Bit 8 – BASEID Base Layer Interrupt Disable
Bit 4 – FIFOERRID Output FIFO Error Interrupt Disable
Bit 3 – ROWID Row Interrupt Disable
Bit 2 – DISPID Powerup/Powerdown Sequence Terminated Interrupt Disable
Bit 1 – DISID LCD Disable Interrupt Disable
Bit 0 – SOFID Start of Frame Interrupt Disable
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
