38.7.95 High-End Overlay U-UV DMA Control Register
| Name: | LCDC_HEOUCTRL |
| Offset: | 0x00000394 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| UDONEIEN | UADDIEN | UDSCRIEN | UDMAIEN | UDFETCH | |||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
Bit 5 – UDONEIEN End of List Interrupt Enable
| Value | Description |
|---|---|
| 0 |
End of list interrupt is disabled. |
| 1 |
End of list interrupt is enabled. |
Bit 4 – UADDIEN Add Head Descriptor to Queue Interrupt Enable
| Value | Description |
|---|---|
| 0 |
Transfer descriptor added to queue interrupt is enabled. |
| 1 |
Transfer descriptor added to queue interrupt is enabled. |
Bit 3 – UDSCRIEN Descriptor Loaded Interrupt Enable
| Value | Description |
|---|---|
| 0 |
Transfer descriptor loaded interrupt is enabled. |
| 1 |
Transfer descriptor loaded interrupt is disabled. |
Bit 2 – UDMAIEN End of DMA Transfer Interrupt Enable
| Value | Description |
|---|---|
| 0 |
DMA transfer completed interrupt is enabled. |
| 1 |
DMA transfer completed interrupt is disabled. |
Bit 0 – UDFETCH Transfer Descriptor Fetch Enable
| Value | Description |
|---|---|
| 0 |
Transfer Descriptor fetch is disabled. |
| 1 |
Transfer Descriptor fetch is enabled. |