38.7.122 High-End Overlay Configuration Register 21
| Name: | LCDC_HEOCFG21 |
| Offset: | 0x00000400 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| XPHI2COEFF3[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| XPHI2COEFF2[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| XPHI2COEFF1[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| XPHI2COEFF0[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 31:24 – XPHI2COEFF3[7:0] Horizontal Coefficient for phase 2 tap 3
Coefficient format is 1 sign bit and 7 fractional bits.
Bits 23:16 – XPHI2COEFF2[7:0] Horizontal Coefficient for phase 2 tap 2
Coefficient format is 1 magnitude bit and 7 fractional bits.
Bits 15:8 – XPHI2COEFF1[7:0] Horizontal Coefficient for phase 2 tap 1
Coefficient format is 1 sign bit and 7 fractional bits.
Bits 7:0 – XPHI2COEFF0[7:0] Horizontal Coefficient for phase 2 tap 0
Coefficient format is 1 sign bit and 7 fractional bits.