The following
configuration values are valid for all listed bit names of this register:
0: The
corresponding interrupt is disabled.
1: The corresponding interrupt is
enabled.
Name:
LCDC_HEOIMR
Offset:
0x00000374
Reset:
0x00000000
Property:
Read-only
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
VOVR
VDONE
VADD
VDSCR
VDMA
Access
R
R
R
R
R
Reset
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
UOVR
UDONE
UADD
UDSCR
UDMA
Access
R
R
R
R
R
Reset
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
OVR
DONE
ADD
DSCR
DMA
Access
R
R
R
R
R
Reset
0
0
0
0
0
Bit 22 – VOVR Overflow for V Chrominance Interrupt
Mask
Bit 21 – VDONE End of List for V Chrominance Component
Mask
Bit 20 – VADD Head Descriptor Loaded for V Chrominance Component
Mask
Bit 19 – VDSCR Descriptor Loaded for V Chrominance Component
Interrupt Mask
Bit 18 – VDMA End of DMA Transfer for V Chrominance Component
Interrupt Mask
Bit 14 – UOVR Overflow for U Chrominance Interrupt
Mask
Bit 13 – UDONE End of List for U or UV Chrominance Component
Mask
Bit 12 – UADD Head Descriptor Loaded for U or UV Chrominance
Component Mask
Bit 11 – UDSCR Descriptor Loaded for U or UV Chrominance Component
Interrupt Mask
Bit 10 – UDMA End of DMA Transfer for U or UV Chrominance
Component Interrupt Mask
Bit 6 – OVR Overflow Interrupt Mask
Bit 5 – DONE End of List Interrupt
Mask
Bit 4 – ADD Head Descriptor Loaded Interrupt
Mask
Bit 3 – DSCR Descriptor Loaded Interrupt
Mask
Bit 2 – DMA End of DMA Transfer Interrupt
Mask
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
