38.7.15 LCD Controller Interrupt Status Register
| Name: | LCDC_LCDISR |
| Offset: | 0x38 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PP | HEO | OVR2 | OVR1 | BASE | |||||
| Access | R | R | R | R | R | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FIFOERR | ROW | DISP | DIS | SOF | |||||
| Access | R | R | R | R | R | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
Bit 13 – PP Post Processing Raw Interrupt Status
| Value | Description |
|---|---|
| 0 |
No Post Processing interrupt detected since last read of LCDC_PPISR |
| 1 |
Indicates that Post Processing interrupt is pending. This flag is reset as soon as the LCDC_PPISR is read. |
Bit 11 – HEO High-End Overlay Raw Interrupt Status
| Value | Description |
|---|---|
| 0 |
No High-End layer interrupt detected since last read of LCDC_HEOISR. |
| 1 |
Indicates that a High-End layer interrupt is pending. This flag is reset as soon as the LCDC_HEOISR is read. |
Bit 10 – OVR2 Overlay 2 Raw Interrupt Status
| Value | Description |
|---|---|
| 0 |
No Overlay 2 layer interrupt detected since last read of LCDC_OVR2ISR. |
| 1 |
Indicates that an Overlay 2 layer interrupt is pending. This flag is reset as soon as the LCDC_OVR2ISR is read. |
Bit 9 – OVR1 Overlay 1 Raw Interrupt Status
| Value | Description |
|---|---|
| 0 |
No Overlay 1 layer interrupt detected since last read of LCDC_OVR1ISR. |
| 1 |
Indicates that an Overlay 1 layer interrupt is pending. This flag is reset as soon as the LCDC_OVR1ISR is read. |
Bit 8 – BASE Base Layer Raw Interrupt Status
| Value | Description |
|---|---|
| 0 | No base layer interrupt detected since last read of LCDC_BASEISR. |
| 1 | Indicates that a base layer interrupt is pending. This flag is reset as soon as the LCDC_BASEISR is read. |
Bit 4 – FIFOERR Output FIFO Error
| Value | Description |
|---|---|
| 0 | No underflow has occurred in the output FIFO since last read of LCDC_LCDISR. |
| 1 | Indicates that an underflow has occurred in the output FIFO. This flag is reset after a read operation. |
Bit 3 – ROW Row Interrupt Status
| Value | Description |
|---|---|
| 0 |
No detection since last read of the LCDC_LCDCISR. |
| 1 |
Indicates that a row event has been detected. This flag is reset after a read operation. |
Bit 2 – DISP Powerup/Powerdown Sequence Terminated Interrupt Status
| Value | Description |
|---|---|
| 0 | Powerup sequence or powerdown sequence has not yet terminated. |
| 1 | Indicates the powerup sequence or powerdown sequence has terminated. This flag is reset after a read operation. |
Bit 1 – DIS LCD Disable Interrupt Status
| Value | Description |
|---|---|
| 0 | Horizontal and vertical timing generator has not yet been disabled. |
| 1 | Indicates that the horizontal and vertical timing generator has been disabled. This flag is reset after a read operation. |
Bit 0 – SOF Start of Frame Interrupt Status
| Value | Description |
|---|---|
| 0 | No detection since last read of LCDC_LCDISR. |
| 1 | Indicates that a start of frame event has been detected. This flag is reset after a read operation. |