38.7.40 Overlay 1 Channel Enable Register
| Name: | LCDC_OVR1CHER |
| Offset: | 0x00000160 |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| A2QEN | UPDATEEN | CHEN | |||||||
| Access | W | W | W | ||||||
| Reset | – | – | – |
Bit 2 – A2QEN Add To Queue Enable
| Value | Description |
|---|---|
| 0 |
No effect |
| 1 |
Indicates that a valid descriptor has been written to memory, its memory location should be written to the DMA head pointer. The A2QSR status bit is set to one, and it is reset by hardware as soon as the descriptor pointed to by the DMA head pointer is added to the list. |
Bit 1 – UPDATEEN Update Overlay Attributes Enable
| Value | Description |
|---|---|
| 0 |
No effect |
| 1 |
Updates window attributes (size, alpha blending, etc.) on the next start of frame. |
Bit 0 – CHEN Channel Enable
| Value | Description |
|---|---|
| 0 |
No effect |
| 1 |
Enables the DMA channel |