The following
configuration values are valid for all listed bit names of this register:
0: The
corresponding interrupt is disabled.
1: The corresponding interrupt is
enabled.
Name:
LCDC_BASEIMR
Offset:
0x00000074
Reset:
0x00000000
Property:
Read-only
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
Access
Reset
Bit
15
14
13
12
11
10
9
8
Access
Reset
Bit
7
6
5
4
3
2
1
0
OVR
DONE
ADD
DSCR
DMA
Access
R
R
R
R
R
Reset
0
0
0
0
0
Bit 6 – OVR Overflow Interrupt Mask
Bit 5 – DONE End of List Interrupt Mask
Bit 4 – ADD Head Descriptor Loaded Interrupt Mask
Bit 3 – DSCR Descriptor Loaded Interrupt Mask
Bit 2 – DMA End of DMA Transfer Interrupt Mask
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