38.7.10 LCD Controller Disable Register
| Name: | LCDC_LCDDIS |
| Offset: | 0x24 |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PWMRST | DISPRST | SYNCRST | CLKRST | ||||||
| Access | W | W | W | W | |||||
| Reset | – | – | – | – |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PWMDIS | DISPDIS | SYNCDIS | CLKDIS | ||||||
| Access | W | W | W | W | |||||
| Reset | – | – | – | – |
Bit 11 – PWMRST LCD Controller PWM Reset
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Resets the PWM module. The duty cycle may be violated. |
Bit 10 – DISPRST LCD Controller DISP Signal Reset
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Resets the DISP signal. |
Bit 9 – SYNCRST LCD Controller Horizontal and Vertical Synchronization Reset
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Resets the timing engine. The horizontal and vertical pulse widths are both violated. |
Bit 8 – CLKRST LCD Controller Clock Reset
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Resets the pixel clock generator module. The pixel clock duty cycle may be violated. |
Bit 3 – PWMDIS LCD Controller Pulse Width Modulation Disable
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Disables the pulse width modulation signal. |
Bit 2 – DISPDIS LCD Controller DISP Signal Disable
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Disables the DISP signal. |
Bit 1 – SYNCDIS LCD Controller Horizontal and Vertical Synchronization Disable
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Disables the synchronization signals after the end of the frame. |
Bit 0 – CLKDIS LCD Controller Pixel Clock Disable
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Disables the pixel clock. |