The following
configuration values are valid for all listed bit names of this register:
0: The
corresponding interrupt is disabled.
1: The corresponding interrupt is
enabled.
Name:
LCDC_LCDIMR
Offset:
0x34
Reset:
0x00000000
Property:
Read-only
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
Access
Reset
Bit
15
14
13
12
11
10
9
8
PPIM
HEOIM
OVR2IM
OVR1IM
BASEIM
Access
R
R
R
R
R
Reset
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
FIFOERRIM
ROWIM
DISPIM
DISIM
SOFIM
Access
R
R
R
R
R
Reset
0
0
0
0
0
Bit 13 – PPIM Post Processing Interrupt
Mask
Bit 11 – HEOIM High-End Overlay Interrupt
Mask
Bit 10 – OVR2IM Overlay 2 Interrupt Mask
Bit 9 – OVR1IM Overlay 1 Interrupt Mask
Bit 8 – BASEIM Base Layer Interrupt Mask
Bit 4 – FIFOERRIM Output FIFO Error Interrupt Mask
Bit 3 – ROWIM Row Interrupt Mask
Bit 2 – DISPIM Powerup/Powerdown Sequence Terminated Interrupt Mask
Bit 1 – DISIM LCD Disable Interrupt Mask
Bit 0 – SOFIM Start of Frame Interrupt Mask
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
