38.7.11 LCD Controller Status Register
| Name: | LCDC_LCDSR |
| Offset: | 0x28 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SIPSTS | PWMSTS | DISPSTS | LCDSTS | CLKSTS | |||||
| Access | R | R | R | R | R | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
Bit 4 – SIPSTS Synchronization In Progress
| Value | Description |
|---|---|
| 0 | Clock domain synchronization is terminated. |
| 1 | Synchronization is in progress. Access to the registers LCDC_LCDCCFG[0..6], LCDC_LCDEN and LCDC_LCDDIS has no effect. |
Bit 3 – PWMSTS LCD Controller PWM Signal Status
| Value | Description |
|---|---|
| 0 | PWM is disabled. |
| 1 | PWM signal is activated. |
Bit 2 – DISPSTS LCD Controller DISP Signal Status
| Value | Description |
|---|---|
| 0 | DISP is disabled. |
| 1 | DISP signal is activated. |
Bit 1 – LCDSTS LCD Controller Synchronization status
| Value | Description |
|---|---|
| 0 | Timing engine is disabled. |
| 1 | Timing engine is running. |
Bit 0 – CLKSTS Clock Status
| Value | Description |
|---|---|
| 0 | Pixel clock is disabled. |
| 1 | Pixel clock is running. |