The following
configuration values are valid for all listed bit names of this register:
0: No effect.
1: Enables the corresponding interrupt.
Name:
LCDC_LCDIER
Offset:
0x2C
Reset:
–
Property:
Write-only
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
Access
Reset
Bit
15
14
13
12
11
10
9
8
PPIE
HEOIE
OVR2IE
OVR1IE
BASEIE
Access
W
W
W
W
W
Reset
–
–
–
–
–
Bit
7
6
5
4
3
2
1
0
FIFOERRIE
ROWIE
DISPIE
DISIE
SOFIE
Access
W
W
W
W
W
Reset
–
–
–
–
–
Bit 13 – PPIE Post Processing Interrupt
Enable
Bit 11 – HEOIE High-End Overlay Interrupt
Enable
Bit 10 – OVR2IE Overlay 2 Interrupt
Enable
Bit 9 – OVR1IE Overlay 1 Interrupt
Enable
Bit 8 – BASEIE Base Layer Interrupt Enable
Bit 4 – FIFOERRIE Output FIFO Error Interrupt Enable
Bit 3 – ROWIE Row Interrupt Enable
Bit 2 – DISPIE Powerup/Powerdown Sequence Terminated Interrupt Enable
Bit 1 – DISIE LCD Disable Interrupt Enable
Bit 0 – SOFIE Start of Frame Interrupt Enable
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
