The following
configuration values are valid for all listed bit names of this register:
0: No effect.
1: Disables the corresponding interrupt.
Name:
LCDC_OVR1IDR
Offset:
0x00000170
Reset:
–
Property:
Write-only
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
Access
Reset
Bit
15
14
13
12
11
10
9
8
Access
Reset
Bit
7
6
5
4
3
2
1
0
OVR
DONE
ADD
DSCR
DMA
Access
W
W
W
W
W
Reset
–
–
–
–
–
Bit 6 – OVR Overflow Interrupt
Disable
Bit 5 – DONE End of List Interrupt
Disable
Bit 4 – ADD Head Descriptor Loaded Interrupt
Disable
Bit 3 – DSCR Descriptor Loaded Interrupt
Disable
Bit 2 – DMA End of DMA Transfer Interrupt
Disable
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
