38.7.51 Overlay 1 Configuration Register 0

Name: LCDC_OVR1CFG0
Offset: 0x0000018C
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
   LOCKDISROTDIS   DLBO 
Access R/WR/WR/W 
Reset 000 
Bit 76543210 
   BLEN[1:0]     
Access R/WR/W 
Reset 00 

Bit 13 – LOCKDIS Hardware Rotation Lock Disable

ValueDescription
0

System bus lock signal is asserted when a rotation is performed.
1

System bus lock signal is cleared when a rotation is performed.

Bit 12 – ROTDIS Hardware Rotation Optimization Disable

ValueDescription
0

Rotation optimization is enabled.
1

Rotation optimization is disabled.

Bit 8 – DLBO Defined Length Burst Only for Channel Bus Transaction

ValueDescription
0

Undefined length INCR burst is used for a burst of 2 and 3 beats.
1

Only defined length burst is used (SINGLE, INCR4, INCR8 and INCR16).

Bits 5:4 – BLEN[1:0] System Bus Burst Length

ValueNameDescription
0 AHB_BLEN_SINGLE

System bus access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats.
1 AHB_BLEN_INCR4

System bus access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. A system bus INCR4 Burst is used. SINGLE, INCR and INCR4 bursts are used. INCR is used for a burst of 2 and 3 beats.
2 AHB_BLEN_INCR8

System bus access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. A system bus INCR8 Burst is used. SINGLE, INCR, INCR4 and INCR8 bursts are used. INCR is used for a burst of 2 and 3 beats.
3 AHB_BLEN_INCR16

System bus access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. A system bus INCR16 Burst is used. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats.