38.7.28 Base Layer Interrupt Status Register
| Name: | LCDC_BASEISR |
| Offset: | 0x00000078 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| OVR | DONE | ADD | DSCR | DMA | |||||
| Access | R | R | R | R | R | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
Bit 6 – OVR Overflow Detected
| Value | Description |
|---|---|
| 0 | No overflow occurred since last read of LCDC_BASEISR |
| 1 | An overflow occurred. This flag is reset after a read operation. |
Bit 5 – DONE End of List Detected
| Value | Description |
|---|---|
| 0 | No End of List condition occurred since last read of LCDC_BASEISR |
| 1 | End of List condition has occurred. This flag is reset after a read operation. |
Bit 4 – ADD Head Descriptor Loaded
| Value | Description |
|---|---|
| 0 | No descriptor has been loaded since last read of LCDC_BASEISR |
| 1 | The descriptor pointed to by the LCDC_BASEHEAD register has been loaded successfully. This flag is reset after a read operation. |
Bit 3 – DSCR DMA Descriptor Loaded
| Value | Description |
|---|---|
| 0 | No descriptor has been loaded since last read of LCDC_BASEISR |
| 1 | A descriptor has been loaded successfully. This flag is reset after a read operation. |
Bit 2 – DMA End of DMA Transfer
| Value | Description |
|---|---|
| 0 | No end of DMA transfer has been detected since last read of LCDC_BASEISR |
| 1 | End of Transfer has been detected. This flag is reset after a read operation. |