2.1.8.5 Calibration Side Effects

Enabling calibration introduces an additional latency of 14 system clock cycles fro each analog‑to‑digital converter (ADC) conversion, which results in a reduction in the maximum achievable sampling rate. Calibration also increases the overall tile count of the design.

The tile count increase depends on the system clock frequency specified in the ASB dialog. If the system clock frequency is greater than 60MHz, the tile count increase is approximately 470 tiles. Otherwise, the increase is approximately 370 tiles.