2.1.16.3 Accessing RTC Registers

When reading the Real Time Counter (RTC) count or match registers, which operate in the XTLCLK clock domain, the corresponding 40‑bit value is first copied into a capture register through clock‑synchronization circuitry. This capture occurs only when the least significant byte (LSB) of the register set is addressed.

After the LSB is accessed, the higher‑order bytes of the same register set can be read in subsequent read cycles. These higher‑order bytes may be read in any order, but they must be read before accessing a different register set to ensure data consistency.

For example, the RTC counter register spans addresses 0x40 through 0x44. To read the full 40‑bit counter value, register 0x40 must be accessed first, followed by registers 0x41, 0x42, 0x43, and 0x44.