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21
SmartTime
21.12
Dialog Boxes
21.12.26
Timing Violations Report Options Dialog Box
21.12.26.2
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SmartPower
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SmartTime
21
Introduction
21.1
Design Flows with SmartTime
21.2
Starting and Closing SmartTime
21.3
SmartTime Components
21.4
SmartTime Constraint Scenario
21.5
Setting SmartTime Options
21.6
SmartTime Tutorial
21.7
SmartTime Constraints Editor
21.8
SmartTime Timing Analyzer
21.9
Advanced Timing Analysis
21.10
Generating Timing Reports
21.11
Timing Concepts
21.12
Dialog Boxes
21.12.1
Add Path Analysis Set Dialog Box
21.12.2
Analysis Set Properties Dialog Box
21.12.3
Edit Filter Set Dialog Box
21.12.4
Select Source Pins for Clock Constraint Dialog Box
21.12.5
Create Clock Constraint Dialog Box
21.12.6
Create Generated Clock Constraint Dialog Box
21.12.7
Customize Analysis View Dialog Box
21.12.8
Manage Clock Domain Dialog Box
21.12.9
Select Generated Clock Source Dialog Box
21.12.10
Select Generated Clock Reference Dialog Box
21.12.11
Select Source or Destination Pins for Constraint Dialog Box
21.12.12
Set False Path Constraint Dialog Box
21.12.13
Set Clock Source Latency Dialog Box
21.12.14
Set Constraint to Disable Timing Arcs Dialog Box
21.12.15
Set Clock-to-Clock Uncertainty Constraint Dialog Box
21.12.16
Set Input Delay Constraint Dialog Box
21.12.17
Set Maximum Delay Constraint Dialog Box
21.12.18
Set Minimum Delay Constraint Dialog Box
21.12.19
Set Multicycle Constraint Dialog Box
21.12.20
Set Output Delay Constraint Dialog Box
21.12.21
SmartTime Options Dialog Box
21.12.22
Store Filter as Analysis Set Dialog Box
21.12.23
Timing Bottleneck Analysis Options Dialog Box
21.12.24
Timing Datasheet Report Options Dialog Box
21.12.25
Timing Report Options Dialog Box
21.12.26
Timing Violations Report Options Dialog Box
21.12.26.1
General
21.12.26.2
Paths
21.12.26.2.1
Display of paths
21.12.26.2.2
Restore Defaults
21.13
Menus, Tools, and Shortcut Keys
21.14
Data Change History – SmartTime
21.15
Constraints by File Format - SDC Command Reference
21.16
Design Object Access Commands
21.17
Glossary
21.18
Revision History
21
Microchip FPGA Support
21
Microchip Information
22
Timer
23
VHDL Vital Simulation
24
Verilog Simulation
25
Technical Support
26
About Microchip
21.12.26.2 Paths
Figure 21-116.
Timing Violations Report - Paths Dialog Box
Rev: A
