11.2.3.2 DMA Channel n Control Register

Note:

Only the original DMACNTn is required to be stored to recover the original DMASRCn and DMADSTn values.
DMACNTn will always be reloaded in Repeated mode transfers, regardless of the state of the RELOAD bit.
The number of transfers executed while CHREQ is set depends on the configuration of TRMODE[1:0].

Legend: r = Reserved bit

Name:	DMACHn
Offset:	0xAB0


Bit	15	14	13	12	11	10	9	8
				Reserved		NULLW	RELOAD	CHREQ
Access				r		R/W	R/W	R/W
Reset				0		0	0	0


Bit	7	6	5	4	3	2	1	0
	SAMODE[1:0]		DAMODE[1:0]		TRMODE[1:0]		SIZE	CHEN
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 12 – Reserved Maintain as ‘`0`’

Bit 10 – NULLW Null Write Mode bit

Value	Description
1	A dummy write is initiated to DMASRCn for every write to DMADSTn
0	No dummy write is initiated

Bit 9 – RELOAD Address and Count Reload bit⁽¹⁾

Value	Description
1	DMASRCn, DMADSTn and DMACNTn registers are reloaded to their previous values upon the start of the next operation
0	DMASRCn, DMADSTn and DMACNTn are not reloaded on the start of the next operation⁽²⁾

Bit 8 – CHREQ DMA Channel Software Request bit⁽³⁾

Value	Description
1	A DMA request is initiated by software; automatically cleared upon completion of a DMA transfer
0	No DMA request is pending

Bits 7:6 – SAMODE[1:0] Source Address Mode Selection bits

Value	Description
11	DMASRCn is used in Peripheral Indirect Addressing and remains unchanged
10	DMASRCn is decremented based on the SIZE bit after a transfer completion
01	DMASRCn is incremented based on the SIZE bit after a transfer completion
00	DMASRCn remains unchanged after a transfer completion

Bits 5:4 – DAMODE[1:0] Destination Address Mode Selection bits

Value	Description
11	DMADSTn is used in Peripheral Indirect Addressing and remains unchanged
10	DMADSTn is decremented based on the SIZE bit after a transfer completion
01	DMADSTn is incremented based on the SIZE bit after a transfer completion
00	DMADSTn remains unchanged after a transfer completion

Bits 3:2 – TRMODE[1:0] Transfer Mode Selection bits

Value	Description
11	Repeated Continuous
10	Continuous
01	Repeated One-Shot
00	One-Shot

Bit 1 – SIZE Data Size Selection bit

Value	Description
1	Byte (8-bit)
0	Word (16-bit)

Bit 0 – CHEN DMA Channel Enable bit

Value	Description
1	The corresponding channel is enabled
0	The corresponding channel is disabled

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