11.2.3.1 DMA Engine Control Register
| Name: | DMACON |
| Offset: | 0xAA8 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DMAEN | DMASIDL | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PRSSEL | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
Bit 15 – DMAEN DMA Module Enable bit
| Value | Description |
|---|---|
| 1 | Enables module |
| 0 | Disables module and terminates all active DMA operation(s) |
Bit 13 – DMASIDL DMA Stop in Idle bit
| Value | Description |
|---|---|
| 1 | DMA continues to run in Idle mode |
| 0 | DMA is disabled in Idle mode |
Bit 0 – PRSSEL Channel Priority Scheme Selection bit
| Value | Description |
|---|---|
| 1 | Round robin scheme |
| 0 | Fixed priority scheme |