11.2.3.3 DMA Channel n Interrupt Register
- Setting these flags in software does not generate an interrupt.
- Testing for address limit violations (DMASRCn or DMADSTn is either greater than DMAH or less than DMAL) is NOT done before the actual access.
| Name: | DMAINTn |
| Offset: | 0xAB2 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DBUFWF | CHSEL[6:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | |||||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| HIGHIF | LOWIF | DONEIF | HALFIF | OVRUNIF | HALFEN | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 |
Bit 15 – DBUFWF DMA Buffered Data Write Flag bit(1)
| Value | Description |
|---|---|
| 1 | The content of the DMA buffer has not been written to the location specified in DMADSTn or DMASRCn in Null Write mode |
| 0 | The content of the DMA buffer has been written to the location specified in DMADSTn or DMASRCn in Null Write mode |
Bits 14:8 – CHSEL[6:0] DMA Channel Trigger Selection bits
Bit 7 – HIGHIF DMA High Address Limit Interrupt Flag bit(1,2)
| Value | Description |
|---|---|
| 1 | The DMA channel has attempted to access an address higher than DMAH or the upper limit of the data RAM space |
| 0 | The DMA channel has not invoked the high address limit interrupt |
Bit 6 – LOWIF DMA Low Address Limit Interrupt Flag bit(1,2)
| Value | Description |
|---|---|
| 1 | The DMA channel has attempted to access the DMA SFR address lower than DMAL, but above the SFR range (07FFh) |
| 0 | The DMA channel has not invoked the low address limit interrupt |
Bit 5 – DONEIF DMA Complete Operation Interrupt Flag bit(1)
| Value | Description |
|---|---|
|
If CHEN = |
|
| 1 | The previous DMA session has ended with completion |
| 0 | The current DMA session has not yet completed |
|
If CHEN = |
|
| 1 | The previous DMA session has ended with completion |
| 0 | The previous DMA session has ended without completion |
Bit 4 – HALFIF DMA 50% Watermark Level Interrupt Flag bit(1)
| Value | Description |
|---|---|
| 1 | DMACNTn has reached the halfway point to 0000h |
| 0 | DMACNTn has not reached the halfway point |
Bit 3 – OVRUNIF DMA Channel Overrun Flag bit(1)
| Value | Description |
|---|---|
| 1 | The DMA channel is triggered while it is still completing the operation based on the previous trigger |
| 0 | The Overrun condition has not occurred |
Bit 0 – HALFEN Halfway Completion Watermark bit
| Value | Description |
|---|---|
| 1 | Interrupts are invoked when DMACNTn has reached its halfway point and at completion |
| 0 | An interrupt is invoked only at the completion of the transfer |