18.1.12 SPIx Underrun Data Register Low
| Name: | SPIxURDTH |
| Offset: | 0x2C6, 0x2E2 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SPIxURDTH[31:24] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SPIxURDTH[23:16] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 15:0 – SPIxURDTH[31:16] SPI Underrun Data bits
These bits are only used when URDTEN = 1. This register holds
the data to transmit when a Transmit Underrun condition occurs.
When the MODE[32:16] or WLENGTH[4:0] bits select 32 to 25-bit data, the SPIx only uses URDATA[31:16]. When the MODE[32:16] or WLENGTH[4:0] bits select 24 to 17-bit data, the SPIx only uses URDATA[23:16].