18.1.1 SPIx Control Register 1 Low
- When AUDEN =
1, this module functions as if CKE =0, regardless of its actual value. - When FRMEN =
1, SSEN is not used. - MCLKEN can only be written when the SPIEN bit =
0. - This channel is not meaningful for DSP/PCM mode as LRC follows FRMSYPW.
| Name: | SPIxCON1L |
| Offset: | 0x2AC, 0x2C8, 0x2E4 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SPIEN | SPISIDL | DISSDO | MODE32 and MODE16[1:0] | SMP | CKE | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SSEN | CKP | MSTEN | DISSDI | DISSCK | MCLKEN | SPIFE | ENHBUF | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 15 – SPIEN SPIx On bit
| Value | Description |
|---|---|
1 | Enables module |
0 | Turns off and resets module, disables clocks, disables interrupt event generation, allows SFR modifications |
Bit 13 – SPISIDL SPIx Stop in Idle Mode bit
| Value | Description |
|---|---|
1 | Halts in CPU Idle mode |
0 | Continues to operate in CPU Idle mode |
Bit 12 – DISSDO Disable SDOx Output Port bit
| Value | Description |
|---|---|
1 | SDOx pin is not used by the module; pin is controlled by port function |
0 | SDOx pin is controlled by the module |
Bits 11:10 – MODE32 and MODE16[1:0] Serial Word Length Select bits(1,4)
| MODE32 | MODE16 | AUDEN | Communication |
|---|---|---|---|
1 | x | 0 | 32-Bit |
0 | 1 | 16-Bit | |
0 | 0 | 8-Bit | |
1 | 1 | 1 | 24-Bit Data, 32-Bit FIFO, 32-Bit Channel/64-Bit Frame |
1 | 0 | 32-Bit Data, 32-Bit FIFO, 32-Bit Channel/64-Bit Frame | |
0 | 1 | 16-Bit Data, 16-Bit FIFO, 32-Bit Channel/64-Bit Frame | |
0 | 0 | 16-Bit FIFO, 16-Bit Channel/32-Bit Frame |
Bit 9 – SMP SPIx Data Input Sample Phase bit
Client Mode:
Input data are always sampled at the middle of data output time, regardless of the SMP setting.
Host Mode:
| Value | Description |
|---|---|
1 |
Input data are sampled at the end of data output time |
0 |
Input data are sampled at the middle of data output time |
Bit 8 – CKE SPIx Clock Edge Select bit(1)
| Value | Description |
|---|---|
1 | Transmit happens on transition from Active Clock state to Idle Clock state |
0 | Transmit happens on transition from Idle Clock state to Active Clock state |
Bit 7 – SSEN Client Select Enable bit (Client mode)(2)
| Value | Description |
|---|---|
1 | SSx pin is used by the macro in Client mode; SSx pin is used as the Client select input |
0 | SSx pin is not used by the macro (SSx pin will be controlled by the port I/O) |
Bit 6 – CKP Clock Polarity Select bit
| Value | Description |
|---|---|
1 | Idle state for clock is a high level; Active state is a low level |
0 | Idle state for clock is a low level; Active state is a high level |
Bit 5 – MSTEN Host Mode Enable bit
| Value | Description |
|---|---|
1 | Host mode |
0 | Client mode |
Bit 4 – DISSDI Disable SDIx Input Port bit
| Value | Description |
|---|---|
1 | SDIx pin is not used by the module; pin is controlled by port function |
0 | SDIx pin is controlled by the module |
Bit 3 – DISSCK Disable SCKx Output Port bit
| Value | Description |
|---|---|
1 | SCKx pin is not used by the module; pin is controlled by port function |
0 | SCKx pin is controlled by the module |
Bit 2 – MCLKEN Host Clock Enable bit(3)
| Value | Description |
|---|---|
1 | REFO is used by the BRG |
0 | PBCLK is used by the BRG |
Bit 1 – SPIFE Frame Sync Pulse Edge Select bit
| Value | Description |
|---|---|
1 | Frame Sync pulse (Idle-to-active edge) coincides with the first bit clock |
0 | Frame Sync pulse (Idle-to-active edge) precedes the first bit clock |
Bit 0 – ENHBUF Enhanced Buffer Enable bit
| Value | Description |
|---|---|
1 | Enhanced Buffer mode is enabled |
0 | Enhanced Buffer mode is disabled |