18.1.9 SPIx Interrupt Mask Register Low
| Name: | SPIxIMSKL |
| Offset: | 0x2C0, 0x2DC, 0x2F8 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| FRMERREN | BUSYEN | SPITUREN | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SRMTEN | SPIROVEN | SPIRBEN | SPITBEN | SPITBFEN | SPIRBFEN | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 12 – FRMERREN Enable Interrupt Events via FRMERR bit
| Value | Description |
|---|---|
1 |
Frame error generates an interrupt event |
0 |
Frame error does not generate an interrupt event |
Bit 11 – BUSYEN Enable Interrupt Events via SPIBUSY bit
| Value | Description |
|---|---|
1 |
SPIBUSY generates an interrupt event |
0 |
SPIBUSY does not generate an interrupt event |
Bit 8 – SPITUREN Enable Interrupt Events via SPITUR bit
| Value | Description |
|---|---|
1 |
Transmit Underrun (TUR) generates an interrupt event |
0 |
Transmit Underrun does not generate an interrupt event |
Bit 7 – SRMTEN Enable Interrupt Events via SRMT bit
| Value | Description |
|---|---|
1 |
Shift Register Empty (SRMT) generates interrupt events |
0 |
Shift Register Empty does not generate interrupt events |
Bit 6 – SPIROVEN Enable Interrupt Events via SPIROV bit
| Value | Description |
|---|---|
1 |
SPIx Receive Overflow (ROV) generates an interrupt event |
0 |
SPIx Receive Overflow does not generate an interrupt event |
Bit 5 – SPIRBEN Enable Interrupt Events via SPIRBE bit
| Value | Description |
|---|---|
1 |
SPIx RX buffer empty generates an interrupt event |
0 |
SPIx RX buffer empty does not generate an interrupt event |
Bit 3 – SPITBEN Enable Interrupt Events via SPITBE bit
| Value | Description |
|---|---|
1 |
SPIx transmit buffer empty generates an interrupt event |
0 |
SPIx transmit buffer empty does not generate an interrupt event |
Bit 1 – SPITBFEN Enable Interrupt Events via SPITBF bit
| Value | Description |
|---|---|
1 |
SPIx transmit buffer full generates an interrupt event |
0 |
SPIx transmit buffer full does not generate an interrupt event |
Bit 0 – SPIRBFEN Enable Interrupt Events via SPIRBF bit
| Value | Description |
|---|---|
1 |
SPIx receive buffer full generates an interrupt event |
0 |
SPIx receive buffer full does not generate an interrupt event |