18.1.6 SPIx Buffer Register Low

Name:	SPIxBUFL
Offset:	0x2B8, 0x2D4


Bit	15	14	13	12	11	10	9	8
	DATA[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	DATA[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 15:0 – DATA[15:0] SPI FIFO Data bits

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