18.1.4 SPIx Status Register Low
- SPITUR is cleared when SPIEN =
0. When IGNTUR =1, SPITUR provides dynamic status of the Transmit Underrun condition, but does not stop RX/TX operation and does not need to be cleared by software.
Legend: C = Clearable bit; HS = Hardware Settable bit; HSC = Hardware Settable/Clearable bit
| Name: | SPIxSTATL |
| Offset: | 0x2B4, 0x2D0, 0x2EC |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| FRMERR | SPIBUSY | SPITUR | |||||||
| Access | R/C/HS | R/HSC | R/HSC | ||||||
| Reset | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SRMT | SPIROV | SPIRBE | SPITBE | SPITBF | SPIRBF | ||||
| Access | R/HSC | R/C/HS | R/HSC | R/HSC | R/HSC | R/HSC | |||
| Reset | 0 | 0 | 1 | 1 | 0 | 0 |
Bit 12 – FRMERR SPIx Frame Error Status bit
| Value | Description |
|---|---|
1 |
Frame error is detected |
0 |
No frame error is detected |
Bit 11 – SPIBUSY SPIx Activity Status bit
| Value | Description |
|---|---|
1 |
Module is currently busy with some transactions |
0 |
No ongoing transactions (at time of read) |
Bit 8 – SPITUR SPIx Transmit Underrun Status bit(1)
| Value | Description |
|---|---|
1 |
Transmit buffer has encountered a Transmit Underrun condition |
0 |
Transmit buffer does not have a Transmit Underrun condition |
Bit 7 – SRMT Shift Register Empty Status bit
| Value | Description |
|---|---|
1 |
No current or pending transactions (i.e., neither SPIxTXB or SPIxTXSR contains data to transmit) |
0 |
Current or pending transactions |
Bit 6 – SPIROV SPIx Receive Overflow Status bit
| Value | Description |
|---|---|
1 |
A new byte/half-word/word has been completely received when the SPIxRXB was full |
0 |
No overflow |
Bit 5 – SPIRBE SPIx RX Buffer Empty Status bit
Standard Buffer Mode:
Automatically set in hardware when SPIxBUF is read from, reading SPIxRXB. Automatically cleared in hardware when SPIx transfers data from SPIxRXSR to SPIxRXB.
Enhanced Buffer Mode:
Indicates RXELM[5:0] = 000000.
| Value | Description |
|---|---|
1 |
RX buffer is empty |
0 |
RX buffer is not empty |
Bit 3 – SPITBE SPIx Transmit Buffer Empty Status bit
Standard Buffer Mode:
Automatically set in hardware when SPIx transfers data from SPIxTXB to SPIxTXSR. Automatically cleared in hardware when SPIxBUF is written, loading SPIxTXB.
Enhanced Buffer Mode:
Indicates TXELM[5:0] = 000000.
| Value | Description |
|---|---|
1 |
SPIxTXB is empty |
0 |
SPIxTXB is not empty |
Bit 1 – SPITBF SPIx Transmit Buffer Full Status bit
Standard Buffer Mode:
Automatically set in hardware when SPIxBUF is written, loading SPIxTXB. Automatically cleared in hardware when SPIx transfers data from SPIxTXB to SPIxTXSR.
Enhanced Buffer Mode:
Indicates TXELM[5:0] = 111111.
| Value | Description |
|---|---|
1 |
SPIxTXB is full |
0 |
SPIxTXB not full |
Bit 0 – SPIRBF SPIx Receive Buffer Full Status bit
Standard Buffer Mode:
Automatically set in hardware when SPIx transfers data from SPIxRXSR to SPIxRXB. Automatically cleared in hardware when SPIxBUF is read from, reading SPIxRXB.
Enhanced Buffer Mode:
Indicates RXELM[5:0] = 111111.
| Value | Description |
|---|---|
1 |
SPIxRXB is full |
0 |
SPIxRXB is not full |