18.1.10 SPIx Interrupt Mask Register High
Note:
- Mask values higher than FIFODEPTH are not valid. The module will not trigger a match for any value in this case.
- RXMSK2 and TXMSK2 bits are only present when FIFODEPTH = 8 or higher.
- RXMSK3 and TXMSK3 bits are only present when FIFODEPTH = 16 or higher.
- RXMSK4 and TXMSK4 bits are only present when FIFODEPTH = 32.
| Name: | SPIxIMSKH |
| Offset: | 0x2C2, 0x2DE, 0x2FA |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| RXWIEN | RXMSK[5:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TXWIEN | TXMSK[5:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bit 15 – RXWIEN Receive Watermark Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Triggers receive buffer element watermark interrupt when RXMSK[5:0] ≤ RXELM[5:0] |
0 |
Disables receive buffer element watermark interrupt |
Bits 13:8 – RXMSK[5:0] RX Buffer Mask bits(1,2,3,4)
RX mask bits; used in conjunction with the RXWIEN bit.
Bit 7 – TXWIEN Transmit Watermark Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Triggers transmit buffer element watermark interrupt when TXMSK[5:0] = TXELM[5:0] |
0 |
Disables transmit buffer element watermark interrupt |
Bits 5:0 – TXMSK[5:0] TX Buffer Mask bits(1,2,3,4)
TX mask bits; used in conjunction with the TXWIEN bit.