16.1.2 QEIx I/O Control Register
Legend: x = Bit is unknown
| Name: | QEIxIOCL |
| Offset: | 0x144, 0x178, 0x544 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| QCAPEN | FLTREN | QFDIV[2:0] | OUTFNC[1:0] | SWPAB | |||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| HOMPOL | IDXPOL | QEBPOL | QEAPOL | HOME | INDEX | QEB | QEA | ||
| Access | R/W | R/W | R/W | R/W | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | x | x | x | x |
Bit 15 – QCAPEN QEIx Position Counter Input Capture Enable bit
| Value | Description |
|---|---|
1 |
HOMEx input event (positive edge) triggers a position capture event (HCAPEN must be cleared) |
0 |
HOMEx input event (positive edge) does not trigger a position capture event |
Bit 14 – FLTREN QEAx/QEBx/INDXx/HOMEx Digital Filter Enable bit
| Value | Description |
|---|---|
1 |
Input pin digital filter is enabled |
0 |
Input pin digital filter is disabled (bypassed) |
Bits 13:11 – QFDIV[2:0] QEAx/QEBx/INDXx/HOMEx Digital Input Filter Clock Divide Select bits
| Value | Description |
|---|---|
111 |
1:256 clock divide |
110 |
1:64 clock divide |
101 |
1:32 clock divide |
100 |
1:16 clock divide |
011 |
1:8 clock divide |
010 |
1:4 clock divide |
001 |
1:2 clock divide |
000 |
1:1 clock divide |
Bits 10:9 – OUTFNC[1:0] QEIx Module Output Function Mode Select bits
| Value | Description |
|---|---|
11 |
The CNTCMPx pin goes high when POSxCNT ≤ QEIxLEC or POSxCNT ≥ QEIxGEC |
10 |
The CNTCMPx pin goes high when POSxCNT ≤ QEIxLEC |
01 |
The CNTCMPx pin goes high when POSxCNT ≥ QEIxGEC |
00 |
Output is disabled |
Bit 8 – SWPAB Swap QEAx and QEBx Inputs bit
| Value | Description |
|---|---|
1 |
QEAx and QEBx are swapped prior to Quadrature Decoder logic |
0 |
QEAx and QEBx are not swapped |
Bit 7 – HOMPOL HOMEx Input Polarity Select bit
| Value | Description |
|---|---|
1 |
Input is inverted |
0 |
Input is not inverted |
Bit 6 – IDXPOL INDXx Input Polarity Select bit
| Value | Description |
|---|---|
1 |
Input is inverted |
0 |
Input is not inverted |
Bit 5 – QEBPOL QEBx Input Polarity Select bit
| Value | Description |
|---|---|
1 |
Input is inverted |
0 |
Input is not inverted |
Bit 4 – QEAPOL QEAx Input Polarity Select bit
| Value | Description |
|---|---|
1 |
Input is inverted |
0 |
Input is not inverted |
Bit 3 – HOME Status of HOMEx Input Pin After Polarity Control bit (read-only)
| Value | Description |
|---|---|
1 |
Pin is at logic ‘ |
0 |
Pin is at logic ‘ |
Bit 2 – INDEX Status of INDXx Input Pin After Polarity Control bit (read-only)
| Value | Description |
|---|---|
1 |
Pin is at logic ‘ |
0 |
Pin is at logic ‘ |
Bit 1 – QEB Status of QEBx Input Pin After Polarity Control and SWPAB Pin Swapping bit (read-only)
| Value | Description |
|---|---|
1 |
Physical pin, QEBx, is at logic ‘ physical pin, QEBx, is at logic ‘ physical pin, QEAx, is at logic ‘ physical pin, QEAx, is at logic ‘ |
0 |
Physical pin, QEBx, is at logic ‘ physical pin, QEBx, is at logic ‘ physical pin, QEAx, is at logic ‘ physical pin, QEAx, is at logic ‘ |
Bit 0 – QEA Status of QEAx Input Pin After Polarity Control and SWPAB Pin Swapping bit (read-only)
| Value | Description |
|---|---|
1 |
Physical pin, QEAx, is at logic ‘ physical pin, QEAx, is at logic ‘ physical pin, QEBx, is at logic ‘ physical pin, QEBx, is at logic ‘ |
0 |
Physical pin, QEAx, is at logic ‘ physical pin, QEAx, is at logic ‘ physical pin, QEBx, is at logic ‘ physical pin, QEBx, is at logic ‘ |